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1/18 december 2004 this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. vnd830pep-e double channel high side driver rev. 4 table 1. general features (*) per each channel cmos compatible inputs open drain status outputs on state open load detection off state open load detection shorted load protection undervoltage and overvoltage shutdown protection against loss of ground very low stand-by current reverse battery protection (**) in compliance with the 2002/95/ec european directive description the vnd830pep-e is a monolithic device designed in stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). figure 1. package active current limitation combined with thermal shutdown and automatic restart protects the device against overload. the device detects open load condition both in on and off state. output shorted to v cc is detected in the off state. device automatically turns off in case of ground pin disconnection. table 2. order codes note: (**) see application schematic at page 9 type r ds(on) i out v cc vnd830pep-e 60 m ? (*) 6.0 a (*) 36 v powersso-24 package tube tape and reel powersso-24 vnd830pep-e VND830PEPTR-E
vnd830pep-e 2/18 figure 2. block diagram table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5k ?; c=100pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v p tot power dissipation t c =25c 54 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c overtemp. 1 v cc gnd input1 output1 overvoltage logic driver 1 status1 v cc clamp undervoltage clamp 1 openload on 1 current limiter 1 openload off 1 output2 driver 2 clamp 2 openload on 2 openload off 2 overtemp. 2 input2 status2 current limiter 2
3/18 vnd830pep-e figure 3. configuration diagram (top view) & suggested connections for unused and n.c. pins figure 4. current and voltage conventions table 4. thermal data note: (*) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m thick) connected to all v cc pins. note: (**) when mounted on a standard single-sided fr-4 board with 8cm 2 of cu (at least 35 m thick) connected to all v cc pins. symbol parameter value unit r thj-case thermal resistance junction-case (max) 2.3 c/w r thj-amb thermal resistance junction-ambient (max) 57 (*) 42 (**) c/w connection / pin status n.c. output input floating x x x x to ground x through 10k ? resistor 1 2 3 4 5 6 output1 output1 output1 output1 input1 status1 gnd v cc 24 23 22 21 20 19 nc nc output1 output1 ta b = v cc 7 8 9 10 11 12 output2 output2 output2 output2 nc v cc status2 nc 18 17 16 15 14 13 nc input2 output2 output2 i s i gnd output 2 v cc gnd status 2 input 2 i out2 i in2 i stat2 v stat2 v in2 v cc v out2 output 1 i out1 v out1 input 1 i in1 status 1 i stat1 v in1 v stat1 v f1 (*) (*) v fn = v ccn - v outn during reverse battery condition
vnd830pep-e 4/18 electrical characteristics (8v8v 60 120 m ? m ? i s supply current off state; v cc =13v; v in =v out =0v off state; v cc =13v; v in =v out =0v; t j =25 c on state; v cc =13v; v in =5v; i out =0a 12 12 5 40 25 7 a a ma i l(off1) off state output current v in =v out =0v 0 50 a i l(off2) off state output current v in =0v; v out =3.5v -75 0 a i l(off3) off state output current v in =v out =0v; v cc =13v; t j =125c 5 a i l(off4) off state output current v in =v out =0v; v cc =13v; t j =25c 3 a symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time r l =6.5 ? from v in rising edge to v out =1.3v 30 s t d(off) turn-on delay time r l =6.5 ? from v in falling edge to v out =11.7v 30 s (dv out / dt) on turn-on voltage slope r l =6.5 ? from v out =1.3v to v out =10.4v see relative diagram v / s (dv out / dt) off turn-off voltage slope r l =6.5 ? from v out =11.7v to v out =1.3v see relative diagram v / s symbol parameter test conditions min typ max unit v f forward on voltage -i out =1.3a; t j =150c 0.6 v symbol parameter test conditions min typ max unit v stat status low output volt- age i stat = 1.6 ma 0.5 v i lstat status leakage current normal operation; v stat = 5v 10 a c stat status pin input capacitance normal operation; v stat = 5v 100 pf v scl status clamp voltage i stat = 1ma i stat = - 1ma 66.8 -0.7 8v v
5/18 vnd830pep-e electrical characteristics (continued) table 9. logic input table 10. protections (see note 1) note: 1. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic sign als must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. table 11. openload detection symbol parameter test conditions min. typ. max. unit v il input low level 1.25 v i il low level input current v in = 1.25v 1 a v ih input high level 3.25 v i ih high level input current v in = 3.25v 10 a v i(hyst) input hysteresis voltage 0.5 v v icl input clamp voltage i in = 1ma i in = -1ma 66.8 -0.7 8v v symbol parameter test conditions min. typ. max. unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload conditions t j >t tsd 20 s i lim current limitation 5.5v vnd830pep-e 6/18 figure 5. figure 6. switching time waveforms v inn v stat n t dol(off) open load status timing (with external pull-up) v inn v stat n overtemp status timing t sdl t sdl i out < i ol v out > v ol t dol(on) t j > t tsd t t v outn v inn 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on)
7/18 vnd830pep-e table 12. truth table table 13. electrical transient requirements on v cc pin conditions input n output n status n normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v oln l h h h l h output current < i oln l h l h h l iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 ? 2 +25 v +50 v +75 v +100 v 0.2 ms 10 ? 3a -25 v -50 v -100 v -150 v 0.1 s 50 ? 3b +25 v +50 v +75 v +100 v 0.1 s 50 ? 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 ? 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 ? iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5c e e e class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
vnd830pep-e 8/18 figure 7. waveforms open load without external pull-up status n input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc status n input n status n status n input n status n input n open load with external pull-up undefined overtemperature input n status n t tsd t r t j output voltage n v cc v ol v ol v cc >v ov
9/18 vnd830pep-e figure 8. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device?s datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k ?) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of c i/os. -v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 20ma; v oh c 4.5v 5k ? r prot 65k ? . recommended r prot value is 10k ?. v cc output2 d ld +5v r prot output1 status1 input1 +5v status2 input2 gnd +5v c r prot r prot r prot d gnd r gnd v gnd
vnd830pep-e 10/18 open load detection in off state off state open load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in the following condition v out =(v pu /(r l +r pu ))r l 11/18 vnd830pep-e figure 10. off state output current figure 11. high level input current figure 12. input clamp voltage figure 13. status low output voltage figure 14. status leakage current figure 15. status clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 il(off1) (a) vcc=36v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (a) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 vstat (v) istat=1.6ma -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 ilstat (a) vstat=5v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vscl (v) istat=1ma
vnd830pep-e 12/18 figure 16. turn-on voltage slope figure 17. on state resistance vs t case figure 18. i lim vs t case figure 19. turn-off voltage slope figure 20. on state resistance vs v cc figure 21. input high level -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 100 200 300 400 500 600 700 800 900 1000 dvout/dt(on) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 20 40 60 80 100 120 140 160 ron (mohm) iout=2a vcc=8v; 13v & 36v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 2 4 6 8 10 12 14 16 18 20 ilim (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 100 150 200 250 300 350 400 450 500 dvout/dt(off) (v/ms) vcc=13v rl=6.5ohm 5 10152025303540 vcc (v) 0 10 20 30 40 50 60 70 80 90 100 110 120 ron (mohm) tc = 1 50 c iout=2a tc=-40c tc=25c -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v)
13/18 vnd830pep-e figure 22. openload on state detection threshold figure 23. input hysteresis voltage figure 24. overvoltage shutdown figure 25. openload off state detection threshold figure 26. input low level figure 27. undervoltage shutdown -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 90 95 100 105 110 115 120 125 130 135 140 iol (ma) vcc=13v vin=5v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 vusd (v)
vnd830pep-e 14/18 powersso-24 thermal data figure 28. powersso-24 pc board figure 29. r thj-amb vs pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 78mm x 78mm, pcb thickness=2mm, cu thickness=35 m, copper areas: from minimum pad lay-out to 8cm 2 ). 40 45 50 55 60 0123456789 rthj_a mb(c/w) pcb cu heatsink area (cm^2)
15/18 vnd830pep-e figure 30. powersso-24 thermal impedance junction ambient single pulse figure 31. thermal fitting model of a double channel hsd in powersso-24 pulse calculation formula table 14. thermal parameter 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth ( c/w) footprint 8 cm 2 area/island (cm 2 ) footprint 8 r1/r7(c/w) 0.1 r2/r8(c/w) 0.9 r3( c/w) 1 r4 (c/w) 4 r5 (c/w) 13.5 r6 (c/w) 37 22 c1/c7(w.s/c) 0.0006 c2/c8(w.s/c) 0.0025 c3 (w.s/c) 0.025 c4 (w.s/c) 0.08 c5 (w.s/c) 0.7 c6 (w.s/c) 3 5 z th r th z thtp 1 ? () + = where t p t ? =
vnd830pep-e 16/18 package mechanical table 15. powersso-24? mechanical data figure 32. powersso-24? package dimensions symbol millimeters min typ max a 2.15 2.47 a2 2.15 2.40 a1 0 0.075 b 0.33 0.51 c 0.23 0.32 d 10.10 10.50 e7.4 7.6 e0.8 e3 8.8 g 0.1 g1 0.06 h 10.1 10.5 h 0.4 l 0.55 0.85 n 10deg x4.1 4.7 y6.5 7.1
17/18 vnd830pep-e revision history table 16. revision history date revision description of changes oct. 2004 1 - first issue. nov. 2004 2 - mechanical data updating. - powersso-24 thermal charact. insertion nov. 2004 3 - pc board copper area correction. dec. 2004 4 - elecrtical charact. insertion. - absolute maximum raitings modification.
vnd830pep-e 18/18 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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